EECS 427 -- VLSI Design I -Technical Information
This page is for people somewhat familiar with VLSI.
The course web page is at http://www.eecs.umich.edu/courses/eecs427
Our final report in Acrobat and Postscript formats.
The chip was designed in a 1.2 micron, two metal, one poly process. It complies with the scalable design rules for MOSIS fabrication.
Size: 5143.90 x 5142.9 microns (approx 5 x 5 millimeters)
Transistors: 72250
Density: 2731 transistors / mm^2
CAD Tools used in design, verification, and simulation:
- Mentor Graphics Design Architect for schematic input
- Mentor Graphics Quicksim for digital simulation
- Mentor Graphics Accusim for analog simulation
- Mentor Graphics IC Station and associated tools for layout, DRC, LVS, parameter extraction
- Cadence Design Systems's Verilog-XL: hardware description language used for control logic
- Design Acceleration, Inc.'s Signalscan for viewing Verilog waveforms
- Cascade Design Automation's EPOCH for synthesis of Verilog, floorplanning, auto place and route, and standard cells
The course web page is at http://www.eecs.umich.edu/courses/eecs427
Our final report in Acrobat and Postscript formats.