Work

Ken

Ken Barr

VMware, Inc.

I am an engineer in the Performance group at VMware in Cambridge, MA. I received my Ph.D. in Electrical Engineering and Computer Science at the Massachusetts Institute of Technology where I was a member of the SCALE group led by Professor Krste Asanovic. My research interests include fast simulation of shared memory multiprocessors, energy efficient systems, performance analysis/visualization, and hardware/software integration.

Contact

email: email address image

Publications / Talks

IEEE Copyright Notice: "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

ACM Copyright Notice: "© ACM, 2000-2006. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. "

  • Summarizing Multiprocessor Program Execution with Versatile, Microarchitecture-Independent Snapshots
    (PDF paper, PDF slides)
    Kenneth C. Barr
    Ph.D. dissertation, Massachusetts Institute of Technology, September, 2006.
  • "Energy Aware Lossless Data Compression"
    (PDF paper)
    Kenneth C. Barr and Krste Asanovic
    Transactions on Computer Systems, 24(3): 250-291, Aug. 2006.
  • "Branch trace compression for snapshot-based simulation"
    Kenneth C. Barr and Krste Asanovic
    (PDF)
    International Symposium on Performance Analysis of Systems and Software, Austin, TX, March 2006.
    Also presented at Boston Area Architecture Workshop, Providence, RI, February 2006. (PDF Slides)
  • "Accelerating a Multiprocessor Simulation with a Memory Timestamp Record"
    Kenneth C. Barr, Heidi Pan, Michael Zhang, and Krste Asanovic
    (PDF)
    International Symposium on Performance Analysis of Systems and Software, Austin, TX, March 2005.
  • "Simulating a Chip Multiprocessor with a Symmetric Multiprocessor"
    Kenneth C. Barr, Ramon Matas-Navarro, Christopher Weaver, Toni Juan and Joel Emer
    (PDF)
    Boston Area Architecture Workshop, Providence, RI, January 2005.
  • "Reducing Power Density through Activity Migration"
    Seongmoo Heo, Kenneth C. Barr, and Krste Asanovic
    (PDF)
    International Symposium on Low Power Electronics and Design (ISLPED), Seoul, Korea, August 2003.
  • "Energy Aware Lossless Data Compression"
    Kenneth C. Barr and Krste Asanovic
    (PDF)
    Best Paper, The First International Conference on Mobile Systems, Applications, and Services, San Francisco, CA, May 2003.
    Also presented at Oxygen Annual Meeting, Cambridge MA, June, 2003
    and Oxygen Quarterly Meeting, Cambridge MA, Oct, 2002
  • "pStore: A Secure Peer-to-Peer Backup System"
    (PDF) (more info)
    Christopher Batten, Kenneth Barr, Arvind Saraf, Stanley Trepetin
    LCS Technical Memo 632, Massachusetts Institute of Technology, Laboratory for Computer Science, October 2002.
  • "Energy Aware Lossless Data Compression"
    (PDF)
    Kenneth C. Barr
    S.M. Thesis, Massachusetts Institute of Technology, September 2002.
  • "Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines"
    (PDF paper)
    Seongmoo Heo, Kenneth Barr, Mark Hampton, and Krste Asanovic
    29th International Symposium on Computer Architecture (ISCA-29), Anchorage, AK, May 2002.
  • "Performance analysis using pipeline visualization"
    (PDF Paper)
    Chris Weaver, Kenneth C. Barr, Eric D. Marsman, Dan Ernst, Todd Austin
    International Symposium on Performance Analysis of Systems and Software, Tucson, AZ, November 2001.

Education

  • Massachusetts Institute of Technology, Cambridge, MA
    Pursuing PhD in Electrical Engineering and Computer Science
    Intel Ph.D. Fellow, 2004-2005
  • Massachusetts Institute of Technology, Cambridge, MA
    SM in Electrical Engineering and Computer Science, October 2002
  • University of Michigan, Ann Arbor, MI
    [Block M]
    BSE in Computer Engineering - summa cum laude, April 2000

Teaching

  • I led tutorials, came up with test and homework questions, and held office hours as a teaching assistant for Computer System Architecture (MIT course 6.823)
  • Since February 2002, I have served as one of the core organizers for 6.186, Mobile Autonomous Systems Lab. MASLab gives me a chance to mentor and learn from teams as they spend four weeks building incredible autonomous robots. Relying on computer vision, having no prereqs, and allowing immense freedom of design makes MASLab unique among robotics contests.
  • I have guided/jump-started/mentored several UROP/MEng students with our group's tester baseboard and with measuring energy in the lab. This, more than most projects, has taught me the value of note-taking and documentation.
  • As a senior at Michigan, I spent a term in the EECS Learning Center as a tutor for EECS 100. This experience was a wakeup call during which I realized the difficulty and importance of teaching fundamental concepts and making sure they are understood by all students.
  • I've taught C programming at Michigan's CampCAEN, a computer camp for high schoolers. It's been exciting to see my students go on to become counselors and EECS majors.
  • As an undergrad, I led several 1-hour workshops demonstrating the use of Maple and Mathematica math software under the auspices of CAEN.

Internships and Work Experience

  • Intel Corporation

    I spent Summer 2004 with Joel Emer and the VSSAD group. I modified the ASIM simulation framework to run on a parallel host (PDF).

    During the summers of 1998-1999, I worked in IAL's Platform Architecture Labs and Internet Systems Labs.

    During my first summer, I investigated and presented the feasibility of dynamically configuring chipsets for optimal performance based on the type of application being run. Wrote software to analyze Rambus traffic for this purpose. Wrote and evaluated software to measure memory latency without a digital logic analyzer. My work was part of the following articles:
    http://developer.intel.com/design/chipsets/820/820perform.htm
    http://www.intel.com/update/issue/issue23.pdf (see page 9 article on the 820)

    I also helped with the characterization of network traffic. Knowing what goes on in the network is important for building useful Network Processors

    Some Intel personalities include: my manager, Frank; group leader (and Intel Fellow) Rick Coulson; and the lab director, Michigan's own Sanjay Panditji.

  • The Dow Chemical Company (Information Systems)

    Designed and implemented a disk-space forecasting tool which reduced costs by eliminating unnecessary speculative purchase of mainframe storage. Wrote Visual Basic utilities to parse and import data from an IBM mainframe for use in Microsoft Access and Excel.

  • While at Michigan, I worked for Craig Strickland at CAEN, CampCAEN and the Millennium Project.

Solutions

People occasionally come to me seeking help with

Coursework

A list of relevant coursework and projects.
Benchmarks ›